1. Field of the Invention
The present invention relates to a semiconductor device having a buried-channel MOS structure in the main surface of a semiconductor substrate and a manufacturing method thereof.
2. Description of the Background Art
With the recent higher integration of semiconductor devices typically including SRAMs and DRAMs, an increasing number of elements are fabricated on a single chip. These elements mostly include, particularly as transistors, field-effect transistors called MOSFETs (Metal Oxide Silicon Field Effect Transistors). The MOSFETs include nMOSFETs (negative MOSFETs) where electrons carry current and pMOSFETs (positive MOSFETs) where holes carry current; the nMOSFETs and pMOSFETs have different electric polarities. Various kinds of circuits are constructed using combinations of nMOSFETs and pMOSFETs.
Known structures of MOSFETs include the surface channel type shown in FIG. 29 and the buried channel type shown in FIG. 30. In the semiconductor device 151 shown in FIG. 29, the semiconductor substrate 100 has source/drain layers 12 separated at an interval (a pair of a source layer and a drain layer are generically called source/drain layers), a punch-through stopper layer 4, and element isolation regions 2 for isolating a plurality of elements. The source/drain layers 12 and the punch-through stopper layer 4 have opposite conductivity types. The semiconductor layer 1 is left under the punch-through stopper layer 4 as part of the semiconductor substrate 100.
A gate electrode 7 faces the space between the source/drain layers 12 with an insulating film 6 interposed between them. The gate electrode 7 has insulator spacers 11 on its side surfaces. Source/drain electrodes 14 (a pair of a source electrode and a drain electrode are generically called source/drain electrodes) are connected to the source/drain layers 12. The gate electrode 7 and the source/drain electrodes 14 are insulated from each other by an insulating layer 13 covering the main surface of, the semiconductor substrate 100. In the semiconductor device 151 thus constructed, the surface portion of the punch-through stopper layer 4 which faces the gate electrode 7 functions as a channel region.
In the semiconductor device 152 shown in FIG. 30, the semiconductor substrate 100 further includes a counter doped layer 5 and a well layer 31, in addition to the source/drain layers 12, punch-through stopper layer 4 and element isolation regions 2. The counter doped layer 5 has the same conductivity type as the source/drain layers 12 and the well layer 31 has the same conductivity type as the punch-through stopper layer 4. The semiconductor layer 1 is left under the well layer 31 as part of the semiconductor substrate 100. In the semiconductor device 152 thus constructed, a region around a PN junction between the counter doped layer 5 and the punch-through stopper layer 4, which faces the gate electrode 7, functions as the channel region. That is, the region spaced from the main surface functions as the channel region. This channel region is called xe2x80x9cburied channel region.xe2x80x9d
In these semiconductor devices 151 and 152, the source/drain layers 12 and the channel region are formed by using impurity ion implantation or by using impurity diffusion from solid phase which contains the impurities. N-type diffusion layers contain N-type impurities such as phosphorus and arsenic and P-type diffusion layers contain P-type impurities such as boron.
Usually, in order to form the gate electrodes with the same material in nMOSFETs and pMOSFETs, nMOSFETs generally use the surface channel type and pMOSFETs use the buried channel type. Accordingly, in most cases, the semiconductor device 151 is formed as an nMOSFET as shown in FIG. 29 and the semiconductor device 152 is formed as a pMOSFET as shown in FIG. 30.
FIGS. 31 to 36 are manufacturing process diagrams showing a method of manufacturing the semiconductor device 152. In the manufacture of the semiconductor device 152, first, the semiconductor substrate 100 is prepared and the element isolation regions 2 are formed in its main surface by LOCOS (Local Oxidation of Silicon) etc. (FIG. 31). Next, phosphorus is implanted to form the N-type well layer 31, and then phosphorus is implanted by ion implantation with an implantation energy of 100 keV to a dose of 6.0xc3x971012 ions/cm2 or more, for example, to form the punch-through stopper layer 4. Subsequently boron is implanted with an implantation energy of 20 keV and, as in the formation of the punch-through stopper layer 4, to a dose of 6.0xc3x971012 ions/cm2 or more, to form the counter doped layer 5 (FIG. 32).
Next, a thermal oxidation is performed to form a 2- to 15-nm-thick film of oxide, as the insulating film 6, on the main surface of the semiconductor substrate 100. Subsequently, polycrystalline silicon 53 containing phosphorus at a concentration of 1xc3x971020/cm3 or more is deposited by LPCVD (Low Pressure CVD) to a thickness of 50 to 150 nm. Next, as an etching mask for formation of the gate electrode, a silicon oxide film 8 is deposited by CVD to a thickness of 20 nm, which is followed by formation of a resist pattern 9 used to form the gate electrode (FIG. 33).
Next, using the resist pattern 9 as a mask, the silicon oxide film 8 and the polycrystalline silicon 53 are selectively etched to form the gate electrode 7 from the polycrystalline silicon 53. The resist pattern 9 is then removed (FIG. 34).
Next, an oxide film is deposited to a thickness of 50 to 100 nm to cover the entirety of the main surface of the semiconductor substrate 100, which is etched back to form the insulator spacers 11 on the side surfaces of the gate electrode 7 (FIG. 35).
Next, boron is implanted into the main surface of the semiconductor substrate 100 under the implant conditions of 5 to 30 keV and 1.0xc3x971015 ions/cm2, thus forming the P+ source/drain layers 12 (FIG. 36). Subsequently, a thermal process is performed at high temperature for activation and repair of crystal defects caused by the ion implantation during formation of the source/drain layers 12. Next, referring to FIG. 30 again, the insulating layer 13 and the source/drain electrodes 14 are formed to complete the semiconductor device 152.
In buried-channel MOSFETs as exemplified by the semiconductor device 152, the advances in miniaturization is incurring the problem that a current which cannot be controlled with the gate voltage is likely to flow in the buried channel region, which is called punch-through current. The punch-through can be effectively suppressed by increasing the impurity concentration in the punch-through stopper layer 4 or by forming a shallower counter doped layer 5 and increasing the impurity concentration thereof.
However, increasing the impurity concentration of the punch-through stopper layer 4 increases the threshold voltage, which leads to another problem of lower driving capability. Further, it is difficult to finally obtain a shallow counter doped layer 5 with higher impurity concentration, since the high-temperature thermal process for activating the source/drain layers 12 which is performed after the formation of the counter doped layer 5 diffuses the impurity in the counter doped layer 5.
The present invention has been made to solve the above-described problems of the conventional art, and an object of the present invention is to provide a semiconductor device which has excellent resistance to punch-through and is suitable for miniaturization and a manufacturing method thereof.
According to a first aspect of the present invention, a semiconductor device comprises: a semiconductor substrate having a main surface and a trench selectively formed in the main surface, the semiconductor substrate comprising a first semiconductor layer of a first conductivity type formed under the trench and a region around the trench, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer on both sides of the trench and exposed on the main surface, a third semiconductor layer of the second conductivity type formed on the first semiconductor layer, the third semiconductor layer being in contact with the bottom of the trench and coupled to the second semiconductor layer, and a fourth semiconductor layer of the first conductivity type selectively formed to cover at least part of the junction between the third semiconductor layer and the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer; the semiconductor device further comprising an insulating film covering a surface of the trench; and an electrode buried in the trench and facing the third semiconductor layer with the insulating film interposed therebetween.
Preferably, according to a second aspect, the semiconductor device further comprises a pair of insulator spacers spaced apart from each other and covering a pair of side surfaces of the trench, wherein the electrode faces the third semiconductor layer in a region interposed between the pair of insulator spacers.
According to a third aspect of the present invention, a semiconductor device comprises a semiconductor substrate having a main surface, the semiconductor substrate comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer, the second semiconductor layer being divided at an interval and selectively exposed on the main surface, a third semiconductor layer of the second conductivity type formed on the surface of the first semiconductor layer, the third semiconductor layer being formed in the interval in the main surface and coupled to the second semiconductor layer, and a fourth semiconductor layer of the first conductivity type selectively formed to cover at least part of the junction between the third semiconductor layer and the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer; the semiconductor device further comprising an insulating layer formed on the main surface and having an opening which opens to the interval in the main surface; a pair of insulator spacers spaced apart from each other and covering a pair of side surfaces of the opening which face each other across the interval; an insulating film covering part of the main surface which is exposed in the opening; and an electrode buried in the opening and facing the third semiconductor layer through the insulating film in a region between the pair of insulator spacers in the opening.
Preferably, according to a fourth aspect, in the semiconductor device, the fourth semiconductor layer is narrower than the third semiconductor layer in the width along the main surface.
Preferably, according to a fifth aspect, in the semiconductor device, the fourth semiconductor layer is spaced apart from the second semiconductor layer.
According to a sixth aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) preparing a semiconductor substrate having a main surface; (b) introducing an impurity of a first conductivity type into the main surface to form a first semiconductor layer of the first conductivity type; (c) introducing an impurity of a second conductivity type into the main surface to form a second semiconductor layer of the second conductivity type on the first semiconductor layer; (d) selectively forming a trench in the main surface so as to divide a region where the second semiconductor layer is exposed on the main surface; (e) introducing an impurity of the second conductivity type through the trench to selectively form a third semiconductor layer of the second conductivity type in such a manner that the third semiconductor layer is in contact with the bottom of the trench and is coupled to the second semiconductor layer; (f) after the step (d) at the earliest, introducing an impurity of the first conductivity type through the trench to selectively form a fourth semiconductor layer of the first conductivity type having a higher impurity concentration than the first semiconductor layer in such a manner that the fourth semiconductor layer covers at least part of the junction between the third semiconductor layer and the first semiconductor layer after the step (e); (g) after the step (d) at the earliest, forming an insulating film to cover a surface of the trench; and (h) after all of the steps (e) to (g), burying an electrode in the trench in such a manner that the electrode faces the third semiconductor layer with the insulating film interposed therebetween.
Preferably, according to a seventh aspect, the semiconductor device manufacturing method further comprises a step (i) of, after the step (e) and before the step (f), forming a pair of insulator spacers covering a pair of side surfaces of the trench, wherein in the step (h), the electrode is buried in the trench so that the electrode faces the third semiconductor layer in a region interposed between the pair of insulator spacers.
According to an eighth aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) preparing a semiconductor substrate having a main surface; (b) introducing an impurity of a first conductivity type into the main surface to form a first semiconductor layer of the first conductivity type; (c) selectively forming a shield on the main surface; (d) after the step (c), introducing an impurity of a second conductivity type into the main surface to selectively form a second semiconductor layer of the second conductivity type in a surface of the first semiconductor layer in such a manner that the second semiconductor layer has an interval right under the shield; (e) after the step (d), forming an insulating layer to cover the main surface with the upper surface of the shield being exposed; (f) removing the shield to selectively form an opening in the insulating layer; (g) introducing an impurity of the second conductivity type through the opening to form a third semiconductor layer of the second conductivity type in the interval in the main surface in the surface of the first semiconductor layer in such a manner that the third semiconductor layer is coupled to the second semiconductor layer; (h) after the step (g), forming a pair of insulator spacers spaced apart from each other and covering a pair of opposite side surfaces of the opening; (i) after the step (f) at the earliest, introducing an impurity of the first conductivity type through the opening to selectively form a fourth semiconductor layer of the first conductivity type having a higher impurity concentration than the first semiconductor layer in such a manner that the fourth semiconductor layer covers at least part of the junction between the third semiconductor layer and the first semiconductor layer; (j) after the step (f) at the earliest, forming an insulating film covering the surface exposed in the opening; and (k) after all of the steps (f) to (j), burying an electrode in the opening in such a manner that the electrode faces the third semiconductor layer through the insulating film in the region interposed between the pair of insulator spacers.
Preferably, according to a ninth aspect, in the semiconductor device manufacturing method, in the step of forming the fourth semiconductor layer, the impurity of the first conductivity type is introduced through the region interposed between the pair of insulator spacers.
Preferably, according to a tenth aspect, in the semiconductor device manufacturing method, in the step of forming the fourth semiconductor layer, the fourth semiconductor layer is formed apart from the second semiconductor layer.
According to the device of the first aspect, an electrode facing the third semiconductor layer is buried in a trench formed in the main surface of the semiconductor substrate and the second semiconductor layer is formed on both sides of the trench. The second semiconductor layer is thus formed in shallower regions than the third semiconductor layer. This suppresses expansion of a depletion layer (i.e. drain depletion layer) from the part of the second semiconductor layer located on one side of the trench (i.e. drain layer) to the part located on the other side of the trench (i.e. source layer), thus preventing the punch-through. Furthermore, the fourth semiconductor layer can be formed in a shallow region since the second semiconductor layer is shallower than the third semiconductor layer, so that the PN junction between the third semiconductor layer and the fourth semiconductor layer exhibits a profile (i.e. impurity concentration distribution) with high concentration and sharp variations. This reduces the threshold voltage and enhances the driving capability, and also enables miniaturization of the device.
According to the device of the second aspect, the presence of the insulator spacers in the trench reduces the length of the channel region (i.e. channel length) formed by parts of the third and fourth semiconductor layers located right under the electrode. As a result, the channel resistance can be reduced to enhance the driving capability of the device.
According to the device of the third aspect, the presence of the insulator spacers in the opening reduces the length of the channel region (i.e. channel length) formed by parts of the third and fourth semiconductor layers located right under the electrode. As a result the channel resistance can be reduced to enhance the driving capability of the device.
According to the device of the fourth aspect, the fourth semiconductor layer is narrower than the third semiconductor layer, so that the parasitic capacitance between the second semiconductor layer and the fourth semiconductor layer can be reduced. This increases the operating speed of the device.
According to the device of the fifth aspect, the second semiconductor layer and the fourth semiconductor layer are spaced apart from each other and therefore they do not form a JP junction. As a result, the junction capacitance which is parasitic capacitance due to PN junction can be reduced to further improve the operating speed of the device.
According to the manufacturing method of the sixth aspect, the third and fourth semiconductor layers are formed after the second semiconductor layer has been formed. Accordingly, it is possible to suppress impurity diffusion in the third and fourth semiconductor layers by eliminating the influence of high-temperature thermal process for activating the impurity in the second semiconductor layer (i.e. source/drain anneal). Therefore the PN junction between the third semiconductor layer and the fourth semiconductor layer exhibits a profile with high concentration and sharp variations. This reduces the threshold voltage and enhances the driving capability, and also enables miniaturization of the device. Furthermore, the source/drain annealing can be performed at higher temperatures to more highly activate the impurity, which reduces the parasitic resistance and thus enhances the driving capability.
Moreover, the electrode facing the third semiconductor layer is buried in the trench formed in the main surface of the semiconductor substrate and the second semiconductor layer is formed on both sides of the trench, and thus the second semiconductor layer is formed in shallower regions than the third semiconductor layer. This provides a device having higher punch-through resistance. Further, the fact that the second semiconductor layer is shallower than the third semiconductor layer is also advantageous in forming a PN junction profile with high concentration and sharp variations between the third semiconductor layer and the fourth semiconductor layer.
According to the manufacturing method of the seventh aspect, a pair of insulator spacers are formed to cover a pair of side surfaces of the trench and the fourth semiconductor layer is formed by introducing the impurity through the region between the pair of insulator spacers. Accordingly the fourth semiconductor layer can be formed in a narrower region to reduce the junction capacitance with the second semiconductor layer. Further, the electrode buried in the trench is formed in the narrower region interposed between the pair of insulator spacers, which reduces the channel length. As a result, the channel resistance can be reduced to enhance the driving capability of the device.
According to the manufacturing method of the eighth aspect, the third and fourth semiconductor layers are formed after the second semiconductor layer has been formed. Accordingly, impurity diffusion in the third and fourth semiconductor layers can be suppressed, without being affected by the high-temperature thermal process for activating the impurity in the second semiconductor layer (i.e. source/drain annealing). Therefore the PN junction between the third semiconductor layer and the fourth semiconductor layer can exhibit a profile with high concentration and sharp variations. This reduces the threshold voltage and enhances the driving capability, and also enables miniaturization of the device. Moreover, the source/drain anneal can be performed at higher temperatures to more highly activate the impurity, which reduces the parasitic resistance, thus enhancing the driving capability.
According to the manufacturing method of the ninth aspect, the fourth semiconductor layer is formed after formation of the pair of insulator spacers by introducing the impurity of the first conductivity type through the region between the pair of insulator spacers. Therefore the fourth semiconductor layer is formed in a narrower region than the third semiconductor layer, which reduces the parasitic capacitance between the second semiconductor layer and the fourth semiconductor layer, thus improving the operating speed of the device.
According to the manufacturing method of the tenth aspect, the second semiconductor layer and the fourth semiconductor layer are separated apart from each other and therefore they do not form a PN junction. This reduces the junction capacitance, i.e. PN-junction-induced parasitic capacitance, thus improving the operating speed of the device.